A historical note: Windows XP 64-bit Edition that was mentioned in the article, was Itanium-specific. It was based on XP kernel while Windows XP x64 Edition (for AMD64 architecture) was based on Windows Server 2003 kernel. Because of that, Windows XP x64 Edition had some significantly different performance characteristics compared to other Windows XP editions. If anything, it was closer to Vista than XP in some aspects.
In approx. 2000 to 2002, 2003 or around then, there was a theoretical dream that Itanium based workstations would become a real mass market thing, but it obviously never caught on.
Intel never made Itanium CPUs cheap enough to realistically purchase and Itanium motherboards never became a thing from the top-10 sized Taiwanese motherboard makers (the same companies that were making really nice boards for the 1 GHz to 1.2 GHz socketed Pentium 3 with 512KB cache and the first generations of Pentium 4).
Also the performance sucked. This was before AMD64 existed on the corporate desktop or home desktop.
It's pretty simple. There was a point in the early 2000s (especially pre-AMD x64) when it was pretty broadly assumed that Itanium from Intel was going to inevitably win given that a 64-bit transition was inevitable (correct) and that it would happen on Intel's terms (incorrect).
I wonder if people are able to get Windows Server 2008 R2 to run on this yet as well. That was the last Windows OS to support Itanium, and it received updates until January 14, 2020.
I think HP had a big investment in Itanium and even sued Oracle to get them to keep supporting Itanium (they had contractually agreed to it, but Itanium was such a dead end...)
I miss itanium. I feel like a madman for saying it, but I do. Something about it is just alluring to me. Alas, the problems were too hard to solve or weren't worth solving anymore
Ironically, it died around the time LLMs/AI started becoming good. I feel like the compiler problems with vliw could be solved to a degree with a purpose built ai
People have tried all kinds of techniques for VLIW, including techniques that are much better than a purpose built AI, AI isn't a magic silver bullet. Fundamentally there's no reason you can't analyse a piece of code to death, and maximally extract parallelism out of it
The fundamental issue is that there simply doesn't exist enough information to be able to extract the necessary parallelism without a rewrite, its the same issue as trying to autovectorise. You can do it to some degree, but it doesn't work in practice to be able to fill out a very wide architecture with reasonable efficacy
The SIMT programming model has proven to be much more successful vs trying to autovectorise or mash things into a VLIW architecture
From memory, Glasgow University CS had serious buy in to VLIW models of computation for a while, predating Itanium. There was good reason for believing it might have some interesting behaviours. I think they worked on languages targetting it, data models, things like reversible computation, long lived processes.
So I feel like I need to write a blog post about this, but succinctly I think there's a good argument to be made that the issue wasn't the compiler despite popular wisdom. I don't even think it was the nature of unpredictable memory access times either as the itanium has a ton of special architectural hardware to handle unpredictable memory accesses (a lot of which are essentially some of the primitives that an OoO core uses for internal bookkeeping, just exposed architecturally).
I just think the arch has a similarity to archs like cell where it was planned for a world without the end of dennard scaling and just stopped making sense when we weren't targeting scaling to 10Ghz consumer CPUs and beyond.
The relatively fixed clock period that makes sense post ~2006 also means that the CPU architecture of that made the most sense ~2006 (Tomasulo OoO cores) continues to make sense, with most of the process gains going to just making bigger, wider cores.
It was also planned for a world where high-end CPUs were differentiated by their ability to run floating-point-heavy workloads with relatively predictable memory access patterns.
The rise of the web—and databases behind it—as the dominant high-end, high-margin workload obsoleted that assumption.
There’s a great presentation floating around where a Compaq-acquired-DEC engineer is trying to justify how great the OpenVMS port from Alpha to Itanium is going, despite benchmarks showing Alpha smoking Itanium running Apache.
I worked for a company that had a fairly large OpenVMS installation and had to make the transition from Alpha to Itanium. It required a considerable amount of work and the early iterations of Itanium did not provide a clear performance improvement over the final Alpha EV7z that we had been using in some GS1280s.
Going by my faulty memory, I'd say it wasn't until Tukwila that it was a clear win over Alpha EV7z. By the time Tukwila arrived, it was pretty clear that Itanium's goose was already cooked.
There was also a long piece by a former Intel chip designer who was incredulous about how much the Itanium team was promising numbers based on a very few hand-scheduled routines for FPU-limited code. I think there’s a solid argument that the design just wasn’t based on a correct understanding of what most CPUs did and over-indexed on the most performance-sensitive HPC code. I once helped run some HPC code on a test Itanium system and even there it was just so easy to fall out of the only patterns which performed well and end up slower than older Pentiums even before factoring price into the evaluation.
> I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".
> Davidson also pointed out two areas where academic research could create a blind spot for architecture developers. First, most contemporary academic research ignored CISC architectures, in part due to the appeal of RISC as an architecture that could be taught in a semester-long course. Since graduate students feed the research pipeline, their initial areas of learning frequently define the future research agenda, which remained focused on RISC. Second, VLIW research tended to be driven by instruction traces generated from scientific or numerical applications. These traces are different in two key ways from the average system-wide non-scientific trace: the numerical traces often have more consistent sequential memory access patterns, and the numerical traces often reflect a greater degree of instruction-level parallelism (ILP). Assuming these traces were typical could lead architecture designers to optimize for cases found more rarely in commercial computing workloads. Fred Weber echoed this latter point in a phone interview. Bhandarkar also speculated that the decision to pursue VLIW was driven by the prejudices of a few researchers, rather than by sound technical analysis.
It's doubly funny knowing that basically nobody bothers doing these kinds of workloads on CPU if they can help it. And everything you have to do to get GPU floating point performance also makes GPUs really, really bad for normal CPU code. Hell, at one point AMD actually was shipping VLIW for shader code...
Even if the magical Itanium compiler did exist, Itanium would have still lost to AMD64. As soon as you introduce anything that doesn't behave in a statically predictable manner (multitasking, or virtualization, or even an application that processes unpredictable input like a web backend or database), your performance drops down to a fraction of what a similarly priced AMD64 chip could do. VLIW is great for some very specific workloads like HPC, but Intel should have never tried to replace x86 with it.
> Ironically, it died around the time LLMs/AI started becoming good.
What?
I think maybe you are confusing Itanium with something else?
Development on itanium stopped in 2013:
> On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same LGA1248 socket and 32 nm process as Poulson, thus effectively halting any further development of Itanium processors.[1]
It's true that it shipped until 2021, but I think you had to already have previous orders to get that.
Itanium never made it into the consumer-class hardware that was XP’s audience. AFAIK, Intel never even published a roadmap for that to happen!
Maybe a proof of concept they shipped as a demonstration of loyalty to Intel?!
Intel never made Itanium CPUs cheap enough to realistically purchase and Itanium motherboards never became a thing from the top-10 sized Taiwanese motherboard makers (the same companies that were making really nice boards for the 1 GHz to 1.2 GHz socketed Pentium 3 with 512KB cache and the first generations of Pentium 4).
Also the performance sucked. This was before AMD64 existed on the corporate desktop or home desktop.
That still seems weird to me. If I had to rely on a PC for high-end work in that period, I wanted the server SKU.
EDIT: there was also an additional patch released in May 2020 according to https://en.wikipedia.org/wiki/Windows_Server_2008_R2#Itanium
Ironically, it died around the time LLMs/AI started becoming good. I feel like the compiler problems with vliw could be solved to a degree with a purpose built ai
The fundamental issue is that there simply doesn't exist enough information to be able to extract the necessary parallelism without a rewrite, its the same issue as trying to autovectorise. You can do it to some degree, but it doesn't work in practice to be able to fill out a very wide architecture with reasonable efficacy
The SIMT programming model has proven to be much more successful vs trying to autovectorise or mash things into a VLIW architecture
I just think the arch has a similarity to archs like cell where it was planned for a world without the end of dennard scaling and just stopped making sense when we weren't targeting scaling to 10Ghz consumer CPUs and beyond.
The relatively fixed clock period that makes sense post ~2006 also means that the CPU architecture of that made the most sense ~2006 (Tomasulo OoO cores) continues to make sense, with most of the process gains going to just making bigger, wider cores.
The rise of the web—and databases behind it—as the dominant high-end, high-margin workload obsoleted that assumption.
There’s a great presentation floating around where a Compaq-acquired-DEC engineer is trying to justify how great the OpenVMS port from Alpha to Itanium is going, despite benchmarks showing Alpha smoking Itanium running Apache.
Going by my faulty memory, I'd say it wasn't until Tukwila that it was a clear win over Alpha EV7z. By the time Tukwila arrived, it was pretty clear that Itanium's goose was already cooked.
> I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".
https://www.sigmicro.org/media/oralhistories/colwell.pdf
> Davidson also pointed out two areas where academic research could create a blind spot for architecture developers. First, most contemporary academic research ignored CISC architectures, in part due to the appeal of RISC as an architecture that could be taught in a semester-long course. Since graduate students feed the research pipeline, their initial areas of learning frequently define the future research agenda, which remained focused on RISC. Second, VLIW research tended to be driven by instruction traces generated from scientific or numerical applications. These traces are different in two key ways from the average system-wide non-scientific trace: the numerical traces often have more consistent sequential memory access patterns, and the numerical traces often reflect a greater degree of instruction-level parallelism (ILP). Assuming these traces were typical could lead architecture designers to optimize for cases found more rarely in commercial computing workloads. Fred Weber echoed this latter point in a phone interview. Bhandarkar also speculated that the decision to pursue VLIW was driven by the prejudices of a few researchers, rather than by sound technical analysis.
http://courses.cs.washington.edu/courses/csep590/06au/projec...
What?
I think maybe you are confusing Itanium with something else?
Development on itanium stopped in 2013:
> On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same LGA1248 socket and 32 nm process as Poulson, thus effectively halting any further development of Itanium processors.[1]
It's true that it shipped until 2021, but I think you had to already have previous orders to get that.
[1]https://en.wikipedia.org/wiki/Itanium