I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level.
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
lol, mb. As in understand it, its that the colors of the bg make it seem like its wires when its not, I'll change the color theme a bit to fix (plz correct me if my understanding is wrong)
Yes, that's the issue: the (thick) solid grey "major axis" lines on the background seemed to be a wire.
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
This is super cool but part of me wishes I could skip to the later levels rather than redo college homework from a decade ago. Maybe that ruins the fun but also slogging through the early levels (especially when the UI is a bit rough around the edges and doesn't support copy paste) isn't fun either.
- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Oh, I didn't notice this capacitor bug, I changed it to add an enable gate for 2.4 (for context, i created 2.4 after 2.7 b/c i thought 2.7 wasn't obvious enough for some ppl). 2.4 kind of needs the enable pin b/c of how my simulation system works.
Yeah, I felt pretty conflicted on the capacitors whilst building, theres actually a note about this in the capacitor info block in later levels, but I couldn't really make a true capacitor compatible with the underlying simulation system I had built (I should have thought it through from the start).
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
Since we're in feedback mode, 2.16 has no BitLineBar reference to feed to the comparators. I had to cheese the level by connecting the "capacitor" outputs straight to the outputs, and it worked.
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
Anyone who likes this should also take a look at: https://store.steampowered.com/app/1444480/Turing_Complete/
At the end you have your own CPU with your own assembly language.
Sadly stuck in early access since forever with some very rough edges
Steam discussions seem to imply there is still something happening https://steamcommunity.com/app/1444480/discussions/0/7674379... But communication is definitely subpar. I completed it a few years ago, was fun but having prior knowledge about digital circuits is a must have in my opinion.
The truth tables are way too hard for me. I need time to think and the 10 seconds is way too fast. If this is intended to be a teaching resource, avoid timers IMHO. It needlessly excludes people.
makes sense, idk if i want to remove times altogether (i personally found it fun + i want the game to be fun for all levels of familiarity), but ill add a modal to explicitly select difficulty level at the start of the racer game, i def agree w/ u overall
You need to have a, "Okay, I've tried 10 times, it's not working, what's the answer?" button. That will help not just us rubes who can't understand, but also in the off chance something is broken and even "correct" answers are being rejected.
makes sense, adding to the next push (in the interim, u can also use the copy circuit button to ask gpt if ur correct or not), also, what level is this? (if u dont mind me asking)
Oh that's what the "copy circuit" button does. I have been trying to paste circuits from previous levels into subsequent ones and wondering what I was doing wrong
This looks really cool, although I personally seem to lack the absolute basic knowledge that is required to make sense of the tutorial messages, so I couldn't even figure out the first level.
Thanks for telling me this, I actually made an act 0 that went through the basics + physics of the pmos and nmos transistors, but i scrapped it b/c i couldn't get it to look like I wanted it to, will add it back
Glad I'm not the only one! I love these kinds of games; played the heck out of Turing Complete and Zachtronics' Engineer of the People... But I'd never heard of 3 state logic until today.
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
I'm confused about a difference in the NMOS and PMOS. The scenario I'm confused about is when the source is VDD and the drain is connected to GND and output.
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
Oh, the drain should only be connected to the output, not drain aswell (irl this would kill one's chip, I'll add a feature to show short-circuiting). on pmos the source should be vdd, on nmos the source should be gnd (this doesn't apply for some later levels, but does for earlier ones).
The 2.13 level ("hex racer") is kind of pain. Apparently I'm not fast enough at dividing/multiplying by 16... when I get something like "convert 0xB3 to decimal"
as a learning resource, it would be great it acronyms were expanded at least once. nmos, pmos, gnd, vdd all in the first 5 seconds or so, and i didnt see anywhere that actually said what those stood for
otherwise, looks polished and fills in a nice niche!
There's the info boxes that it could be added to, that way it is always available at a mouse click.
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
I had an arc 0 where it went through some of these topics more in depth and explained them, deleted it b/c i couldn't get the UI to look right. I've pushed a bandaid that should fix this, but ill bring in arc 0 (it seems this is a popular request) after polishing it (ill also make it optional)
Layout appears unusable on my phone on Firefox Android (both portrait and landscape). Necessary elements seem to get hidden behind others. Not sure if I'm even supposed to be able to play it without kB&m though lol :)
This is a brilliant way to visualize complex hardware architecture. As someone working on web-based image processing having a deeper mental model of how the underlying hardware handles these tasks is incredibly helpful. Truly a learn-by-doing masterpiece.
if you solve a level, then press "next level", then solve that next level - then it still shows the original level (I think it just gets hidden below the new one and then reappears after a solve?)
A nice game, though the truth table lighting round is pretty punishing! Big contrast to the circuit building part where you can take your time. Personally I'd drop the time requirements from that quiz section.
lol, I hadn't seen that video before but its a good one. Na, this is the guide to comp arch that will (hopefully) end all instances of toil over documentation for any sort of processor when learning
So, is there anything about GPU's in here right now?
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
Not at the moment unfortunately, I've actually completed a good chunk of the GPU levels, but I think ppl will need to do act 2 and 3 for it to make sense
Any easy way to make this usable on mobile? In portrait mode things are unreadable, zoom and scrolling do not work. Landscape is even worse as everything is out of view (and zoom/scroll do not work).
This would be such a good game for introducing students to digital technology! This is so fun! We just had to draw them by hand back in the dark ages of the 2010s.
100% agree - the way that you have the very subtle arrows on the transistor drains that show the actual current flow is really smart too. I struggled with visualizing the current flow in undergrad for an embarrassingly long time.
It's always nice to see educational games like that.
A lot of new learners (like me) are just looking at the high level stuff, where the computer "just works"...
Yeah, nand game was part of the inspiration, I felt that it was good but was a bit plain UI/UX wise and obfuscated / simplified some things that it shouldn't have
PWAs have matured a lot — the gap with native apps is much smaller than people think, especially on Android where install prompts work reliably. One thing I appreciate about browser-based games specifically is that they sidestep the distribution problem entirely.
Love it, thanks! Would you mind making it possible for me to see my "circuit" after running the tests? Currently, I can't go back to the circuit I created.
I haven't pushed to github (Will do this soon), but I believe that i've fixed the issue (also, by wanna fix this bug I meant I want to fix this bug, (but would def also appreciate help if ur interested, the mechanics of this game ended up being a bit more complex than I initially envisioned lol))
No problem. I am currently on the third level I think and my laptop fan ramps up, so I closed the tab and it stopped. Also, how can I delete e.g. transistors again?
I see, I'll try to reduce the load, i'm using canvas 2d so that could be causing it. you can delete by selecting then pressing the delete button (will also allow right click to delete in the next push, since i do this for wires)
We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.
Yeah, I had added it to make it compatible w/ my simulation system, just changed how I was handling the levels altogether, if it still has 3 try doing a hard refresh (Ctrl + Shift + R on windows, cmd + shift + R on macos)
Launching on Product Hunt is useful for a burst of early feedback, but the retention from PH users is usually low — they're browsers, not committed users. Better to get 10 people who really need the thing than 500 upvotes.
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...
Some comments:
- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
Thanks, I appreciate all the feedback, fixes coming in the next push
Ive added this to the HN Arcade! https://hnarcade.com/games/games/mvidia
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
otherwise, looks polished and fills in a nice niche!
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
- Made timed minigames optional (e.g. binary tables)
- Added 7 (optional) intro levels to walk through pmos and nmos transistors
- Fixed the bug in the capacitor levels
- Changed editor bg to use dots instead of lines to fix wire confusion
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.
Well done and keep it up :)
also it kept showing the same table to me like 4 times
G0 = D0 AND SEL
G1 = NOT SEL
G2 = D1 AND G1
G0 -> Ans
G2 -> Ans
Edit: Confirmed fixed.
I don't see any button labeled that
We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.