Die yield can depend on redundancy and sensitivity to process variation.
Column/row redundancy for SRAM arrays is common and multicore designs provide core redundancy. Theoretically even out-of-order scheduler entries and functional units could be disabled. SIMD width variability could provide another means of tolerating defects and/or variation while providing a sellable result.
If a usable/sellable die only needs to reach half of the best frequency or half the best case energy efficiency, yield can be higher than if nothing less than 95% of best is worthwhile. If better dies can be sold at higher profit, the economics change. Durability is also a variable that can be tuned (e.g., "The BubbleWrap many-core: Popping cores for sequential acceleration" https://scholar.google.com/scholar?cluster=13412927692517066... ).
Yield does not seem to be simply a matter of defects per square centimeter. At least so it appears to this computer architecture enthusiast.
Depends on how big they are, what layer they land on, what they’re composed of. I was a semiconductor process engineer for a few years, and honestly the worst damage came from people, and not in the “people shed dust everywhere” sense, but in the “people do dumb things” sense. Like when the robot goes bonkers and you have to manually recover a wafer, so you just grab it with your fingers, slot it back in the carrier, and send the lot off to cleans after processing the rest through on a different machine. We would have whole lots with elevated defects because people did stuff like this.
The defect math is interesting, but process uniformity is more of a killer than the author gives it credit for. Fantastic amounts of ingenuity go into showerhead design, chamber design, and minute changes to process conditions, not to mention maintenance practices. We’d like to pretend the pattern and the process are orthogonal, but they’re coupled, and you might need to run 5C colder for one product versus another simply because the material exposed by the pattern loads the chamber differently. And how about water spots? Wet processing leaves water spots, just like you might see after washing your dishes. Huge source of defects, and once again pattern dependent. Patterning usually leaves alternating areas of hydrophilic and hydrophobic material, and you have to somehow prevent water from beading up anywhere. Sure, it starts out deionized, but it’s got plenty of junk in it after rinsing your wafers off.
Column/row redundancy for SRAM arrays is common and multicore designs provide core redundancy. Theoretically even out-of-order scheduler entries and functional units could be disabled. SIMD width variability could provide another means of tolerating defects and/or variation while providing a sellable result.
If a usable/sellable die only needs to reach half of the best frequency or half the best case energy efficiency, yield can be higher than if nothing less than 95% of best is worthwhile. If better dies can be sold at higher profit, the economics change. Durability is also a variable that can be tuned (e.g., "The BubbleWrap many-core: Popping cores for sequential acceleration" https://scholar.google.com/scholar?cluster=13412927692517066... ).
Yield does not seem to be simply a matter of defects per square centimeter. At least so it appears to this computer architecture enthusiast.