TinyTapeout (https://tinytapeout.com/) is fantastic. I submitted three simple designs: one as a part of TinyTapeout 1, and a couple more in TinyTapeout 2, and now waiting for physical chips mounted on a debug board to arrive.
Matt Venn and the TinyTapout community are very friendly to beginners. I highly encourage people to participate in the upcoming TinyTapeout 3 run. They even have a visual editor, if people don't want to mess with Verilog and prefer direct drawing of logic gates: https://wokwi.com/projects/339800239192932947
Last time there was something on this I recall a flood of comments saying this was impossible unless you had a million bucks, so I'm glad to see even within some reasonable limits there's something like this! Yay!
It was never million bucks. There were always businesses offering square millimeter of silicon for few thousands euro on an older technology. Design service might go into millions if one can’t do it by himself though.
No, some universities were sponsoring these back in the day. You could really order 2 chips with 6 square millimeters in total. Economically not viable at all, but good enough for final thesis. And the university also provided design tools making things easier.
The sponsors for the project are footing most of the bill, mostly in an attempt to grow the space. A commercial product trying to do this, will indeed need to sink a few million bucks into something like this.
Can you do it in 1000 logic gates, in a size of 150 x 170 um?
There are very few things that are more complex than toys which fit in that space. It's primarily a learning opportunity, not a hack to build a product.
Also, most of the hard work in Wi-Fi and GPS modules is not in receiving the binary radio signal but in the protocols to decode it. For wifi, the 802.11 protocol would require your PHY to provide at the very least the orthogonal frequency-division multiplexing, but you're probably expecting something closer to a Wiznet chip that provides the fundamental stack available from eg. the lwIP project.
Yeah this is a hard limit - but also in the TT2 world it multiplexes its pins between TT projects through a scan chain - this effectively means that update times on pins are in the sub MHz domain - so anything you are building will be slow. Also there are only 8 input pins and 8 output ones (and 2 of those input pins are reset and clock, so really 6 input pins).
As I understand it there will be a TT3 and the way pins happen will likely greatly change - more pins and faster everything
Well, the question was: can you do analog designs? Designing your own transistors, not relying on logic gates library. That's what full custom means.
That opens the door to less conventional stuff, such as CMOS imagers, memories, RF/Analog designs, etc. Obviously the available space and I/O are going to be limitting factors.
Regarding Wi-Fi, I was thinking of some of the RF frontend for a project such as [1]. I am not extremely knowledgeable about RF, so that would be a learning opportunity. I imagine it to be mostly carrier generation and multiplexing, the higher layers are doable on an off-the-shelf FPGA.
That said, Wi-Fi is a simple target, but maybe not the most interesting one. That's the first full-custom application example I thought of.
Can you do it in 1000 logic gates, in a size of 150 x 170 um?
There are very few things that are more complex than toys which fit in that space. It's primarily a learning opportunity, not a hack to build a product.
Regarding the other comment about there only being 14 pins, if I was determined to try putting an early CPU replica in there, I would try multiplexing the pins. The 4004 is already in a 16-pin package, with 2 of those being power and ground.
I built a 4-bit 4004 equivalent for TT2 and then an 8-bit equivalent - sort of 8051 level sort of stuff - quite doable, the hard bit is the tiny bus interface
How do people interface these with a computer? Is there some standard way to build it into a card that plugs into the computer and can have software connect using drivers of some sort?
For instance if you had programmed the ASIC with a function that replaced something done in software, how do you divert the data from the relevant step over to the ASIC and back again? Can they keep up with CPUs (or is it the other way round?)
In the case of Tiny Tapeout, it's unlikely you'd be replacing any kind of general purpose compute task. The process node and size of the ASIC just isn't really sufficient.
It's a toy to demystify the ASIC design process. You can get a bare chip produced or for more money, get the same chip already soldered down onto a PCB. There's a good render of it in this article: https://www.eenewseurope.com/en/tinytapeout-boost-for-open-s... - it has a 7-segment display and some pin breakouts.
If you were to build an ASIC to replace a general purpose computing function, you'd usually either synthesize PCI Express or USB functionality into your design, design a breakout PCB to interface with the bus, and then write a device driver to interface with whatever endpoints your device presented, or add a microcontroller of some kind in "front" of the device that talked PCI Express or USB and translated into a "lower level" chip communication method like I2C, SPI, or even raw parallel address/data/clock lines.
I would be very surprised if even a fourth of the list you just posted could fit inside the design contraints of tiny tapeout. You have about 1000 digital logic gates max as per their FAQ.
I don't think it's fair to knock it like that. This isn't going inside some industrial project. This is a hobbyist who went from zero(!) to ASIC.
It's a completely ridiculous list. The blogpost is about designing a 2 tap filter, not a CPU, so even if there wasn't a gate limit the design wouldn't have those things.
Matt Venn and the TinyTapout community are very friendly to beginners. I highly encourage people to participate in the upcoming TinyTapeout 3 run. They even have a visual editor, if people don't want to mess with Verilog and prefer direct drawing of logic gates: https://wokwi.com/projects/339800239192932947
My design was rather simple [1], compared to others I saw. I designed a tool to explore the Hamming error-correcting code.
[1] https://abdullahkhalid.com/blog/2022/Aug/31/designing-a-chip...
What if you prefer direct drawing of the mask layers?
https://m.youtube.com/watch?v=V9xCa4RNfCM
We have FPGAs for (most) logic stuff, but what if I wanted a tiny, power-efficient RF (Wi-Fi or GPS for instance) chip?
There are very few things that are more complex than toys which fit in that space. It's primarily a learning opportunity, not a hack to build a product.
Also, most of the hard work in Wi-Fi and GPS modules is not in receiving the binary radio signal but in the protocols to decode it. For wifi, the 802.11 protocol would require your PHY to provide at the very least the orthogonal frequency-division multiplexing, but you're probably expecting something closer to a Wiznet chip that provides the fundamental stack available from eg. the lwIP project.
As I understand it there will be a TT3 and the way pins happen will likely greatly change - more pins and faster everything
That opens the door to less conventional stuff, such as CMOS imagers, memories, RF/Analog designs, etc. Obviously the available space and I/O are going to be limitting factors.
Regarding Wi-Fi, I was thinking of some of the RF frontend for a project such as [1]. I am not extremely knowledgeable about RF, so that would be a learning opportunity. I imagine it to be mostly carrier generation and multiplexing, the higher layers are doable on an off-the-shelf FPGA.
That said, Wi-Fi is a simple target, but maybe not the most interesting one. That's the first full-custom application example I thought of.
[1]: https://github.com/open-sdr/openwifi
There are very few things that are more complex than toys which fit in that space. It's primarily a learning opportunity, not a hack to build a product.
A 6502 with 3.5k transistors might fit comfortably in that size: https://news.ycombinator.com/item?id=11703995
A 4004 has 2.3k transistors and may also fit.
Regarding the other comment about there only being 14 pins, if I was determined to try putting an early CPU replica in there, I would try multiplexing the pins. The 4004 is already in a 16-pin package, with 2 of those being power and ground.
For instance if you had programmed the ASIC with a function that replaced something done in software, how do you divert the data from the relevant step over to the ASIC and back again? Can they keep up with CPUs (or is it the other way round?)
It's a toy to demystify the ASIC design process. You can get a bare chip produced or for more money, get the same chip already soldered down onto a PCB. There's a good render of it in this article: https://www.eenewseurope.com/en/tinytapeout-boost-for-open-s... - it has a 7-segment display and some pin breakouts.
If you were to build an ASIC to replace a general purpose computing function, you'd usually either synthesize PCI Express or USB functionality into your design, design a breakout PCB to interface with the bus, and then write a device driver to interface with whatever endpoints your device presented, or add a microcontroller of some kind in "front" of the device that talked PCI Express or USB and translated into a "lower level" chip communication method like I2C, SPI, or even raw parallel address/data/clock lines.
Low-latency is achieved with a Carry Look-Ahead Adder and includes subtraction.
O(n^2) naïve multiplier design, whereas O(n^1.58) is easily achieved and extendable to MAC capabilities.
Then there's a divider unit.
Microcoding.
Pipelining.
Pipelining with branch prediction.
Floating point.
Superscalar with reservation stations.
Register aliasing.
Hyperthreading (slack time virtual cores).
VLIW.
L1 caching.
L2 caching.
L0 caching.
SMP.
L3 caching.
And add your mask easter egg here.
I don't think it's fair to knock it like that. This isn't going inside some industrial project. This is a hobbyist who went from zero(!) to ASIC.